DESIGN AND IMPLEMENTATION OF A LOW-VOLTAGE 2.4-GHZ CMOS RF RECEIVER FRONT-END FOR WIRELESS COMMUNICATION
This paper presents the design of a 1.5 V CMOS RF receiver front-end system which contains a low noise amplifier (LNA) with band pass filter and a down conversion mixer. An inter-stage matching network is added between the common-source and common-gate transistors in the LNA’s first stage to further lower the noise and enhance the overall gain. An inductor is used in this inter-stage matching network because of the extra capacitive of MOSFETs in the LNA. The maximum gain achieved of this LNA is 15 dB. The single square-law structure was implemented for this low power consumption and high linearity mixer. From the measured results, the whole receiver provides a conversion gain of 8.5 dB at 2.4 GHz with LO power input -3.5 dBm. The power dissipation of this front-end is 9 mW .
Liou, Wan-Rone; Yeh, Mei-Ling; Tsai, Chun-An; and Chang, Shun-Hsyung
"DESIGN AND IMPLEMENTATION OF A LOW-VOLTAGE 2.4-GHZ CMOS RF RECEIVER FRONT-END FOR WIRELESS COMMUNICATION,"
Journal of Marine Science and Technology: Vol. 13:
3, Article 2.
Available at: https://jmstt.ntou.edu.tw/journal/vol13/iss3/2